1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to an electrically programmable and erasable non-volatile semiconductor memory device in which a plurality of bytes can be programmed/erased at one time, and to a method of operating the same.
2. Description of the Background Art
FIG. 19 is a cross sectional view of a general electrically programmable/erasable non-volatile semiconductor memory device (hereinafter referred to as an EEPROM).
Referring to FIG. 19, the memory cell structure of the EEPROM will be briefly described. N.sup.+ impurity regions 2, 3 and 10 are formed spaced apart by a prescribed distance on a main surface of a P.sup.- semiconductor substrate 1. A gate electrode 4 is formed on a region between impurity regions 2 and 3 with an insulating film formed of oxide interposed. A floating gate 7 electrically insulated by a very thin oxide film (tunnelling oxide film) 6 of about 100.ANG. is formed on impurity region 3, and a control gate 8 with interposed insulating film is formed thereon. Thus, a memory transistor (two-layered gate transistor) 9 having a two-layered gate structure is provided.
In the EEPROM, 1 bit of memory cell is formed by a selecting transistor and a memory transistor 9. Impurity region 2 is connected to a bit terminal BL, a gate electrode 4 is connected to a word terminal WL, and impurity region 10 is connected to a source terminal SL. Control gate 8 is connected to a control gate terminal CG.
In an actual memory cell array, gate electrode 4 is connected to a word line for selection in the row direction of the memory cell array, and impurity region 2 is connected to a bit line for selection in the column direction. Impurity region 10 is connected to a source line.
The operation of the memory cell shown in FIG. 19 will be described.
A high voltage Vpp (generally, about 12 V) is applied to the bit terminal BL and word terminal WL of the memory cell, 0 V is applied to the control gate terminal CG and the source terminal SL is set to a high impedance state. Then, a very strong electric field is applied from floating gate 7 to the oxide film 6 in the direction of impurity region 3, and electrons are drawn from floating gate 7 to impurity region 3 because of tunneling phenomenon. Consequently, the potential of floating gate 7 attains positive, and two-layered gate transistor 9 turns on even if 0 V is applied to control gate 8. More specifically, two-layered gate transistor 9 is set to a depression state. This state is called a programmed state which corresponds to data "0".
A high voltage Vpp (generally, 12 V) is applied to control gate terminal CG of the memory cell, 0 V is applied to the bit terminal BL and a high level signal is applied to the word terminal WL. The source terminal SL is applied with 0 V or it is set to a high impedance state. Then a very strong electric field is applied to oxide film 6 from impurity region 3 in the direction of floating gate 7, and electrons are introduced from impurity region 3 to floating gate 7 because of tunneling phenomenon. Consequently, the potential of floating gate 7 attains negative, and two-layered gate transistor 9 does not turn on when 0 V is applied to control gate 8. Namely, two-layered gate transistors 9 is set to an enhancement state. This state is called an erased state, which corresponds to data "1".
The above described erasing and programming operations of the memory cell are collectively defined as writing.
In order to read information (data) written in the memory cell, the potential of the word terminal WL is set to a high level, and 0 V is generally applied to the control gate terminal CG, and whether or not a current flows between the bit terminal BL and source terminal SL is detected.
FIG. 20 shows relation between a current ICE11 flowing between the bit terminal BL and the source terminal SL and the voltage VCG applied to the control gate terminal CG at the programmed state and the erased state. If VCG=0 V and the current flows, it means that the memory cell is at the programmed state, and if the current does not flow, it can be determined that the memory cell is at the erased state.
FIG. 21 is a block diagram showing a chip structure of a general EEPROM, and FIG. 22 is a schematic diagram showing specific circuit structure of the memory cell array and the periphery.
Referring to FIG. 21, a memory cell array 11 includes a plurality of memory cells arranged in a matrix. A plurality of word lines are arranged corresponding to a plurality of rows of the memory cell. A plurality of bit lines are arranged corresponding to a plurality of columns of the memory cells. Address signals for selecting addresses in memory cell array 11 are input through address terminals A0 to Ak to a X address buffer 12 and a Y address buffer 13. A X decoder 14 receives an output signal from X address buffer 12 and selects one word line from the plurality of word lines. A Y decoder 15 receives an output signal from Y address buffer 13 and selects a bit line corresponding to 1 data from the plurality of bit lines.
A Y gate 18 receives an output signal from Y decoder 15, and connects the selected bit line to a write driver 16 and to a sense amplifier 17. An I/O buffer 19 inputs an input data applied from data input/output terminals D0 to D7 to write driver 16, or outputs output data applied from sense amplifier 17 to data input/output terminals D0 to D7. Write driver 16 transmits the input data to the bit line in memory cell array 11 through Y gate 18, and further writes the data to a column latch group 20 through a transfer gate group 21. Sense amplifier 17 detects whether or not the selected memory cell is at the programmed state or at the erased state.
A Vpp switch group 22 applies a high voltage to the bit line in memory cell array 11 in accordance with the data latched in column latch group 20. A charge pump 23 generates a high voltage from an external power supply which is necessary at writing. An erasure/program timing control circuit 24 controls timing of the erasing and programming operations.
An output enable terminal OE receives an output enable signal designating whether it is an output enabled state or not; a chip enable terminal CE receives a chip enable signal designating whether or not it is a chip active state or not; and a write enable terminal WE receives a write enable signal designating whether it is a write enable state or not. A write/read control circuit controls chip mode in response to the output enable signal, the chip enable signal and the write enable signal.
The circuit structure of the memory cell array 11 and the periphery thereof will be described in detail with reference to FIG. 22.
In memory cell array 11, a plurality of word lines WL1 to WLn are arranged corresponding to a plurality of rows of memory cells, and a plurality of bit lines are arranged corresponding to a plurality of columns of memory cells. A plurality of control gates CG1 to CGn are arranged corresponding to the plurality of rows of the memory cells. The plurality of bit lines are classified into bytes 1 to m each including 8 bit lines BL0 to BL7. All the memory cells (memory cells of the bytes 1 to m) connected to one word line are called a page.
Column latch group 20 includes a plurality of column latches 200, transfer gate group 21 includes a plurality of transfer gate 210, and Vpp switch group 22 includes a plurality Vpp switches 220.
In order to enable collective erasure/programming page by page, one column latch 200 and one Vpp switch 220 are connected to each bit line. A Vpp switch 230 for applying a high voltage to control gates CG1 to CGn is connected to a control gate activating line CGA. The control gate activating line CGA is arranged parallel to bit lines BL0 to BL7. Y decoder 15 is connected to m Y gate lines Y1 to Ym corresponding to the bytes 1 to m. Y gate 18 includes m sets of transfer gates G1 to Gm corresponding to bytes 1 to m. Y gate lines Y1 to Ym are respectively connected to transfer gates G1 to Gm.
A series of erasing/programming operation of the EEPROM shown in FIGS. 21 and 22 will be described with reference to the timing chart of FIG. 23.
In FIG. 23, the reference character T1 shows a write cycle for writing externally input write data to a prescribed column latch 200, T2 shows an erasing cycle for setting all memory cells of the page selected by the word line to the erased state, and T3 shows a program cycle for collectively programming the memory cells of the page selected by the word line in accordance with the write data latched in column latch 200.